Designing of a reversible fault tolerant booth multiplier

Authors

  • Md M Rahman Department of Computer Science and Engineering, University of Dhaka, Dhaka
  • Md M Hossain Department of Computer Science and Engineering, University of Dhaka, Dhaka
  • Lafifa Jamal Department of Robotics and Mechatronics Engineering, University of Dhaka, Dhaka
  • S Nowrin Department of Computer Science and Engineering, East West University, Dhaka

DOI:

https://doi.org/10.3329/bjsir.v53i3.38266

Keywords:

Reversible logic circuit, Fault tolerant circuit, Reversible booth multiplier, Quantum cost, Garbage output

Abstract

Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. This paper presents the design of a reversible fault tolerant booth multiplier which can multiply both signed and unsigned numbers. The proposed circuit tolerant designed using only fault tolerant reversible gates. Thus the entire scheme inherently becomes fault tolerant. Several theorems on the numbers of gates, garbage outputs, quantum cost of the proposed design have been presented to show the efficiency of the design. The result analysis shows that the proposed design is optimized in terms of all cost parameters. The simulation of the proposed circuit verifies the correctness of the circuit.

Bangladesh J. Sci. Ind. Res.53(3), 199-204, 2018

Downloads

Download data is not yet available.
Abstract
761
PDF
628

Downloads

Published

2018-09-18

How to Cite

Rahman, M. M., Hossain, M. M., Jamal, L., & Nowrin, S. (2018). Designing of a reversible fault tolerant booth multiplier. Bangladesh Journal of Scientific and Industrial Research, 53(3), 199–204. https://doi.org/10.3329/bjsir.v53i3.38266

Issue

Section

Articles