Realization of Inverse Active Filters Using Single Current Differencing Buffered Amplifier

The authors introduce a new single current differencing buffered amplifier (CDBA) based inverse filter configuration. By appropriate selection of admittances, different inverse filter circuits like inverse high-pass (IHP) circuit, inverse low-pass (ILP) circuit, inverse bandreject (IBR) circuit and inverse band-pass (IBP) circuit can be realized from the same configuration. The capacitors used here are grounded/virtually grounded for all the realizations. The performances of the proposed filters have been judged by using CMOS structure of CDBA with TSMC 0.35 μm technology as well as by using the available IC of current feedback operational amplifier (CFOA) i.e. AD844 based CDBA. The simulation results agreed well with the theoretical results. Monte-Carlo simulation has also been performed to check the robustness of the proposed configuration.


Introduction
Inverse filters which have an inverse transfer function of the original system are needed for correcting electrical signal distortions caused by the transmission system or signal processors and are used in control systems, communication and instrumentation [1,2]. Though there are several techniques for obtaining inverse digital filtering; only a few circuits are known for realizing continuous-time analog inverse filters. A single fourterminal floating nuller (FTFN) based inverse filter circuit has been reported by Wang and Lee [1], but the circuit is suitable only for all pass filter response. Also, it requires floating capacitor for its realization. Again, the single FTFN based inverse low-pass filter, introduced by Chipipop and Surakampontorn [2], uses floating capacitor and comparatively large number of resistors. However, the topology proposed by Abuelma'atti [3] is capable of realizing all the five inverse filter responses using single FTFN, but it is unfit for IC implementation as it uses floating capacitor. Using current feedback operational amplifier (CFOA) as an active building block, few inverse active filters [4][5][6][7] have been reported but multiple CFOAs are needed for all of them. Further, the filters of Patil and Sharma [7] have the disadvantage of using floating capacitor and large number of resistors. The filter circuits (one each for ILP, IBP and IHP response) proposed by Herencsar et al. [8] require three differential difference current conveyors (DDCCs). Tsukutani et al. [9] introduced three inverse filter circuits, one each for IHP, ILP and IBP filter, but their circuits need three/four operational transconductance amplifiers (OTAs). Contrariwise, the inverse filter circuits based on second generation current conveyors (CCIIs) [10,11] have the limitations of excessive use of active building blocks and resistors. P. Kumar et al. [12] reported a unified filter topology to realize IHP, ILP, IBP and IBR filters, but it employs four voltage differencing transconductance amplifiers (VDTAs). Operational transresistance amplifier (OTRA) has also been employed to implement inverse filters [13][14][15]. However, these filters use two OTRAs and comparatively large number of passive elements.
Presently, a new active block namely current differencing buffered amplifier (CDBA) has been presented by Acar and Ozoguz. It offers all the advantages of current mode techniques and can be operated in several megahertz frequency range. The parasitic capacitance does not exist in this block as its input terminals are virtually grounded [16]. Furthermore, CDBA offers a low impedance voltage mode output, which is very needful for easy cascading. Various analog circuits such as inductor [16], multiplier [17], filter [18], oscillator [19] etc. are available using this versatile active building block.
Although, few attempts have already been made to realize inverse active filters by using CDBA as an active block [20][21][22][23], these circuits have some drawbacks. The inverse filter configuration reported by Nasir and Ahmad [20] has the limitation that it cannot realize IBR filter response. Furthermore, two CDBAs are necessary to implement this configuration. By contrast, Pandey et al. [21] introduced a topology which can realize all the inverse filter functions, but this topology also requires two CDBAs. Another inverse filter configuration has been presented by Bhagat et al. [22] employing two CDBAs. However, this configuration exhibits IBR and IAP filters only. Again, Bhagat et al. [23] reported an inverse filter topology using two CDBAs, but this design is only for ILP, IHP and IBP filter realizations.
In this paper, we propose a new single CDBA based inverse filter configuration which realizes inverse high-pass (IHP), inverse low-pass (ILP), inverse band-pass (IBP) and inverse band-reject (IBR) through the selection of proper admittances. The capacitors are grounded or virtually grounded in all the proposed functions. PSPICE simulation has been carried out by using CMOS as well as AD844 (commercially available IC) structure of CDBA for practical validation of the configuration. Simulation results are satisfactory. Robustness of the structure has been confirmed by Monte-Carlo analysis. The comparison of the reported inverse filter configuration with various previously proposed works are shown in Table 1.

Number of capacitors (C)
Standard filter functions

CDBA
CDBA is a current processing analog active building block which has greater linearity, large dynamic range, wide bandwidth etc. Furthermore, CDBA has no parasitic capacitances due to internally grounded input terminals [16]. Fig. 1(a) shows the circuit symbol of the CDBA, where p and n are the low impedance input terminals, w is low impedance output terminal and z is the high impedance output terminal [17]. The equivalent circuit of the CDBA is shown in Fig. 1(b). The port characteristics of this block can be expressed as = = 0, = and = -. The possible CMOS [17] and AD844 [19] based CDBA are depicted in Figs. 2(a) and 2(b) respectively.

The proposed circuit configuration
The proposed generalized configuration for realizing various inverse filters is shown in Fig. 3. This structure uses single CDBA and six admittances. The transfer function of the circuit of Fig. 3 obtained by routine analysis can be expressed as: If we choose the admittances, such that , and , then the N(s) can be expressed as: (2) The required denominator functions can be obtained by appropriate selection of admittances for , and as shown in Table 2. The transfer functions of various inverse filters are depicted in Table 3. It is clear from Table 3 that the IHP, ILP, IBP and IBR filter responses can be realized from the proposed configuration.

Non-Ideal and Sensitivity Analysis
Practically, the effect of voltage and current tracking errors of CDBA will affect the performances of the proposed inverse filter responses. The non-ideal characteristic equation of CDBA is rewritten through a matrix, given in Eq. (4).
where , and denote the non-ideal port transfer ratios of the CDBA. Reanalyzing the designed circuit, taking into consideration of the non-ideal characteristic equation of CDBA, the revised transfer functions for the filter responses can be expressed as given in Table 4.
From the Eq. (5), it may be concluded that the parameters and Q for all the responses remain unchanged under non-ideal conditions. The sensitivity analysis of and Q for the reported structure can be written as: Eq. (6) ensures that the sensitivities of and Q with respect to different passive elements do not exceed ½ in magnitude.

Parasitic Analysis
Involving the different parasitics, the model of CDBA is shown in Fig. 4. The parasitic resistances , and appear in series at the port p, n and w, respectively, whereas a resistance in parallel with a capacitance appears at the z-port [19]. Reanalyzing the reported circuit, taking into consideration the parasitics of CDBA, the revised transfer functions for the filter responses are depicted in Table 5.  It is clear from Table 5 that the transfer functions of the filters are affected by the nonidealities of CDBA. The so caused deviation from the ideal behaviour can be kept less if the values of all external resistors are kept much smaller than but much higher than , . Likewise, the values of all external capacitors are selected much higher than . Hence, all these parasitic components will be absorbed and they will not affect the circuit parameters.

Simulation Results
PSPICE simulation software has been used for practical verification of the proposed configuration. Initially, the functionality of the proposed circuit has been tested by using CMOS structure of CDBA [17]. For supporting hardware implementation of the designed filters, the CDBA block has also been realized employing market available ICs AD844 [19] and the simulation results for the same have been presented later.

Simulation results using CMOS structure of CDBA
The CMOS version of CDBA used for the purpose of simulations has been shown in Fig.  2(a) [17]. TSMC 0.35 µm technology has been used for this purpose. The aspect ratios of all the transistors used in Fig. 2(a) are given in Table 6 [17]. The supply voltages are chosen as ± 2.5 V. The chosen values of the capacitors and resistors for various filter responses are presented in Table 7. The ideal and simulated frequency response of IHP, ILP, IBP and IBR filters are depicted from Figs. 5(a) to 5(d), respectively.   The -tuning ( = ) responses for the inverse band-reject filter for a particular Q value (Q = ½) are displayed in Fig. 6. The values of capacitors, resistors and corresponding values of are shown in Table 8. In order to determine the variation of centre frequency of IBR filter due to resistors and capacitors tolerance, the Monte Carlo analysis has been carried out. The analysis is done for 100 samples and tolerance is considered 5 % for resistors and capacitors which is shown in Fig. 7. It depicts that the center frequency varies from a minimum value 952.191 kHz to a maximum value 1.05042 MHz with standard deviation 17.2461 kHz. In order to inspect the dynamic range of the filter in their pass band, the output noise for IHP filter has been determined through PSPICE simulation. The variation of output noise within pass band frequencies is demonstrated in Fig. 8, which depicts that noise is in considerable limit. For examining the transient analysis, a sinusoidal input of 100 kHz has been applied at the input terminal of the IBR filter and the obtained curves without significant distortion are depicted in Fig. 9. The IBR response of the proposed configuration has been tested for linearity by noting down the variations of total harmonic distortion (THD) with respect to amplitude of input signal. The result has been shown in Fig. 10. It is obtained from Fig. 10 that THD is increasing from 0.49 % to 2.59 % for the variation of input signal amplitude from 50 mV to 400 mV. From these simulation results it is concluded that the circuit can work excellently.

Simulation results using IC AD844
The performance of all the filter responses has also been verified by using IC AD844 structure of CDBA with ± 10 V supply voltages. The implementation of CDBA using two AD844 ICs is shown in Fig. 2(b). The values of , , and , , are selected according to Table 7. The simulated frequency response of IHP, ILP, IBP and IBR filters are depicted from Figs. 11(a) to 11(d) respectively.     The tuning of the inverse band-pass filter for Q = ½ is shown in Fig. 12. The selected capacitor, resistor values and the corresponding values of are shown in Table  9. To demonstrate the time domain behavior, a sinusoidal signal of 100 kHz, 100 mVp is applied at the IBR filter as input voltage. The input and output curves are depicted in Fig.  13. It is seen that the magnitude of output voltage is equal to input voltage. Fig. 14 depicts the THD variations of the IBR filter response with input signal amplitude. It is found that the THD is almost constant for the input range between 50 mV and 400 mV.  It is found that the PSPICE simulation responses for both the CMOS and AD844 structure of CDBA are in close agreement with the theoretical results.

Conclusion
We have reported a configuration of inverse filter using single CDBA block. Different filter responses can be realized by selecting proper passive elements. The workability of the proposed configuration has been verified using PSPICE simulation with CMOS structure of CDBA implemented with TSMC 0.35 µm process parameters. This configuration has also been tested through CDBA implemented with two AD844 ICs. The simulations results are in close agreement with theoretical prediction. The total harmonic distortion is found to be less than 2.59 % for the IBR filter response when simulated by CMOS based CDBA structure. For AD844 based CDBA structure, it is less than 2.04 %.